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Testing FPGA implementation of HaplotypeCaller (PairHMM)
We are two researchers from the Politecnico di Milano.
We are trying to test the FPGA implementation of the HaplotypeCaller (PairHMM) on GATK 3.8-0-ge9d806836, using a Terasic DE5a-Net (Arria 10, 10AX115N3F45I2SG).
According to the version highlights for GATK 3.8 (https://gatkforums.broadinstitute.org/gatk/discussion/10063/version-highlights-for-gatk-version-3-8) FPGA support was added to pairHMM, and it should be used if the appropriate hardware is detected.
However, from our tests it seems that the CPU implementation is being used instead. Is there a way to enforce the usage of the FPGA implementation?
Chiara & Alberto